1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly to a shift register that employs only a thin film transistor of the same type channel and has a level shifter built-in. And, the present invention relates to a scanning driver, a data driver and a liquid crystal display having the shift register.
2. Description of the Related Art
Generally, a liquid crystal display LCD displays a picture using an electric field to control the light transmittance of a liquid crystal. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit which drives the liquid crystal display panel. Within the liquid crystal display panel, gate lines and data lines are arranged so as to cross each other, and liquid crystal cells are positioned at intersections between the gate lines and the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode which applies the electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain terminals of a thin film transistor acting as a switching device, to the data lines. The gate terminal of the thin film transistor is connected to the gate lines.
The driving circuit includes a gate driver which drives the gate lines, and a data driver which drives the data lines. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel. Whenever any one of the gate lines is supplied with a gate signal, the data driver applies a video signal to corresponding ones of the data lines. A picture is displayed by applying an electric field between the pixel electrode and the common electrode in accordance with a video signal for each liquid crystal in the LCD.
Thin film transistors used in LCDs are classified into amorphous silicon type and polycrystalline silicon types, depending upon whether the semiconductor layer in the transistor is made from amorphous silicon or polycrystalline silicon.
Pixel density in LCDs using amorphous silicon type thin film transistors is relatively low because the amorphous silicon has a relatively small charge mobility. Further, use of the amorphous silicon type thin film transistor is disadvantageous in that it results in higher manufacturing costs of the LCD as peripheral driving circuits, such as the gate driver and the data driver, need to be manufactured separately and mounted in the liquid crystal display panel. On the other hand, LCDs may be manufactured at a relatively low cost using polycrystalline silicon type thin film transistors. Polycrystalline silicon type thin film transistors have a high charge mobility and therefore are used to create relatively high a pixel densities in LCDs. Polycrystalline silicon thin film transistors may also be formed with peripheral driving circuits that are buried and mounted in the liquid crystal display panel. Accordingly, an LCD employing a polycrystalline silicon type thin film transistor will be used in further discussion.
FIG. 1 schematically illustrates a configuration of an LCD employing conventional polycrystalline silicon type thin film transistors.
Referring to FIG. 1, the LCD includes a liquid crystal display panel 10 provided with a picture display area 12, data and gate shift register 14 and 16, respectively, a sampling switching array 15, a printed circuit board PCB 20 having a control chip 22 integrated with control circuitry and a data drive IC and a level shifter array 24 mounted thereon, and a flexible printed circuit FPC film 18 connecting the liquid crystal display panel 10 to the PCB 20.
The picture display area 12 displays a picture by a matrix of liquid crystal cells LC. Each of the liquid crystal cells LC is a switching device connected at an intersection between a gate line GL and a data line DL, which includes an thin film transistor TFT made from polycrystalline silicon. Since the thin film transistor TFT is made from polycrystalline silicon having a charge mobility (a hundred times larger than amorphous silicon) yielding a fast response speed, the liquid crystal cells LC are driven in a point sequence manner. The data lines DL receive video signals from the sampling switch array 15 driven with the data shift register 14. The gate lines GL receive scanning signals from the gate shift register 16.
The data shift register 14 includes a plurality of stages, the output terminals of which are connected to the sampling switches of the sampling switch array 15, respectively. The stages, as shown in FIG. 2, are connected in cascade and shift a source start pulse from the control chip 22 to sequentially apply sampling signals to the sampling switches.
More specifically, the stages ST1 to STn, shown in FIG. 2, are connected to an input line of a start pulse SP in cascade, and connected to three clock signal supplying lines of four-phase clock signal (C1 to C4) supplying lines, respectively. The four phase clock signals C1 to C4 are sequentially fed in a phase-delayed manner by one clock as shown in FIG. 3. Each of the stages ST1 to STn shifts the start pulse SP by one clock with the aid of three clock pulses from the clock signals C1 to C4 to output it. Signals SO1 to SOn, outputted from each of the stages ST1 to STn of the shift register, are applied as sampling signals and applied as a start pulse of the next stage.
The gate shift register 16 includes a plurality of stages, the output terminals of which are connected to the gate lines GL, respectively. The stages, as shown in FIG. 2, are connected in cascade and shift a start pulse from the control chip 22 to sequentially apply scanning pulses to the gate lines GL.
The sampling switch array 15 has an output terminal connected to each of the data lines DL and includes a plurality of sampling switches (not shown) driven with a sampling signal from the data shift register 14. The sampling switches sequentially sample video signals from the control chip 22 in response to said sampling signal to apply them to the data lines DL.
In this way, the picture display area 12 and the data shift register 14, the sampling switching array 15 and the gate shift register 16, which are included in the liquid crystal display panel 10, are formed in the same process since the polycrystalline silicon is employed. In this case, if the thin film transistors TFT in the liquid crystal display panel 10 are composed of only the transistors of the same type, i.e., NMOS or PMOS thin film transistors, the manufacturing cost can be reduced more than when they are composed of CMOS thin film transistors. Because there are included both P and N channels in case of using the CMOS thin film transistors, it is advantageous that the driving voltage has a wide range and it is easier to make an integrated circuit, however, there is a disadvantage that the manufacturing cost is high and the reliability is low since a number of processes are required. Accordingly, liquid crystal display panels 10 tend to be developed toward the use of only the PMOS or NMOS thin film transistor which reduces the number of the process to lower the manufacturing cost and has higher reliability relatively.
A control circuit (not shown) included in the control chip 22 sends video data applied from the exterior to the data drive IC (not shown) and provides driving control signals required for the data shift register 14 and the gate shift register 16. The data drive IC (not shown) converts the video data from the control circuit (not shown) into a video signal acting as an analog signal to apply it, via the FPC film 18, to the sampling switch array 15.
The level shifter array 24 increases swing widths of driving control signals (i.e., clock signal, etc.) inputted from the control circuit and applies them to the data shift register 14 and the gate shift register 16. For example, the level shifter array 24 allows a clock signal, which is generated from the control circuit and has a swing voltage below 10V, to be level-shifted so as to have a swing width of 10V or more (including a negative voltage) and outputs it. This is because a pulse having a swing width of 10V or more should be supplied in order to drive the thin film transistor formed in the liquid crystal display panel 10.
In other words, if the liquid crystal display panel 10 includes PMOS thin film transistors, then a driving pulse for driving the PMOS thin film transistors included in the sampling switch array 15 and the pixel area 12 is required to have a swing width of 10V or more in a negative direction. In order to provide such a driving pulse, a pulse having a swing width of 10V or more in a negative direction must be applied to the gate and data shift registers 14 and 16 as the clock signal. If the external circuit is implemented with a signal chip such as the control chip 22, a clock signal having a swing width within 10V may be easily produced, but a voltage having a swing width greater than 10V or with a negative value is produced with difficulty. In other words, it is difficult to ensure device characteristics while generating a voltage having a swing width more than 10V or a negative voltage and, hence, to manufacture an IC on a single chip. Accordingly, in the related art, the level shifter array 24, used for level-shifting a driving pulse of 10V to have a swing width of 10V or more including a negative voltage, is implemented using a separate chip mounted on the PCB 20. This configuration is disadvantageous that an external circuit mounted on the PCB 20 is made to be compact with great difficulty. Furthermore, since a clock signal including positive and negative voltages and having a swing width of 10V or more must be applied from the external circuit to the data shift register 14 and the gate shift register 16 of the liquid crystal display panel 10, a problem of a large power consumption is encountered.